Start SPARTAN3E

Switch_Button_Pin

Verilog Program:


module test1(a, b, c);
input a,b;
output c;

and  g1(c, a, b);



endmodule







1. Start ISE Design Tool
2. File -> New Project
3. Set both location and Working Directory to T:\
4. Type "demo" after "Name: " -> click on next.
5. Set up project settings:
   Family: Spartan3E
   Device: XC3S500E
   Package: FG320
   Speed:   -4

   Click on Next, and then click on Finish.

6. Click on New File icon on the menu, choose "Text File" -> OK
7. Enter verilog program and save it as test1.v
8. In the Hierarchy window, right click on mouse, and choose add source,
   Click on test1.v in the popup window, then click on open.

9. In the hierarchy window on the left, right click on the test1 symbol,
   choose "New Source" in the popup window.
   Select "Implementation Constraints File",
   and enter "test1_pin" as File name.
   Click on Next, and then click on Finish.
   
10.   
   Edit User Constraint File as following:

   NET "a" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
   NET "b" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;

   NET "c" LOC = "F12";
   

11.Click on  "+" symbol next to "Configure Target Device",
   and then click on Manage Configuration Project (iMPACT).

12. Double click on Boundary Scan.
13. In the right side window, right click on mouse to select cable setup.
    Choose "Platform Cable USB/II". ( You only need to setup cable once )
    Choose OK.

14. In the right side window, right click on mouse to select "Initialize Chain".
15. Click on open "test1.bit" file when the XC3S500E chip is in green color
16. Click on bypass when the XCF04S chip is in green color
17. Click on bypass when the XC2C64A chip is in green color
18. Next, you'll see Devices1 is highlighted in the Boundary-Scan window. Click on OK.

19. Next, right click on the XC2S500E green color icon, choose "program"
    to download the design onto the FPGA