The character LCD uses a four-bit data interface. The display data connections are also
shared with the SF_D<11:8> signals on the StrataFlash PROM. As shown in Table below, the
FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and
LCD_RW signals.
Table: FPGA Control for StrataFlash and LCD
| SF_CE0 | LCD_RW | Function |
| 1 | 1 | The FPGA reads from the character LCD. |
| 0 | 0 | The FPGA accesses the StrataFlash PROM. |